library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 

entity counter is 
  
  port ( 
    clk   : in  std_logic; 
    reset : in  std_logic; 
    cout  : out std_logic_vector(6 downto 0)); 

end counter; 

architecture behave of counter is 
signal cout_int : std_logic_vector(3 downto 0); 
begin  -- behave 
  with cout_int select   --       abcdefg 
  cout <= "1111110" when "0000", 
          "0110000" when "0001", 
          "1101101" when "0010", 
          "1111001" when "0011", 
          "0110011" when "0100", 
          "1011011" when "0101", 
          "1011111" when "0110", 
          "1110000" when "0111", 
          "1111111" when "1000", 
          "1111011" when "1001", 
          "1110111" when "1010", 
          "0011111" when "1011", 
          "1001110" when "1100", 
          "0111101" when "1101", 
          "1001111" when "1110", 
          "1000111" when "1111", 
          (others => 'X') when others; 

  process (clk, reset) 
  begin  -- process 
    if reset = '0' then                 -- asynchronous reset (active low) 
      cout_int <= (others => '0'); 
    elsif clk'event and clk = '1' then  -- rising clock edge 
      cout_int <= cout_int + 1; 
    end if; 
  end process; 

end behave;